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IMAGE SENSORS
FTT1010-M Frame Transfer CCD Image Sensor
Product specification File under Image Sensors 1999 September 21
Philips Semiconductors
TRAD
Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
* * * * * * * * * * * * * *
1-inch optical format 1M active pixels (1024H x 1024V) Progressive scan Excellent anti-blooming Variable electronic shuttering Square pixel structure H and V binning 100% optical fill factor High dynamic range (>72dB) Description High sensitivity Low dark current and fixed pattern noise Low read-out noise Data rate up to 2 x 40 MHz Mirrored and split read-out
The FTT 1010-M is a monochrome progressive-scan frame-transfer image sensor offering 1K x 1K pixels at 30 frames per second through a single output buffer. The combination of high speed and a high linear dynamic range (>12 true bits at room temperature without cooling) makes this device the perfect solution for high-end real time medical X-ray, scientific and industrial applications. A second output can either be used for mirrored images, or can be read out simultaneously with the other output to double the frame rate. The device structure is shown in figure 1.
Device structure
Optical size: Chip size: Pixel size: Active pixels: Total no. of pixels: Optical black pixels: Timing pixels: Dummy register cells: Optical black lines: 12.288 mm (H) x 12.288 mm (V) 14.572 mm (H) x 26.508 mm (V) 12 m x 12 m 1024 (H) x 1024 (V) 1072 (H) x 1030 (V) Left: 20 Right: 20 Left: 4 Right: 4 Left: 7 Right: 7 Bottom: 6 Top: 6
Z
6 black lines Image Section
Y
1024 active lines 4 20 2060 lines
20 4 1024 active pixels
Storage Section
W
Output 7 amplifier
6 black lines 1072 cells Output register
X
7
Figure 1 - Device structure
1999 September
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Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Architecture of the FTT1010-M
The FTT1010-M consists of a shielded storage section and an open image section. Both sections are electronically the same and have the same cell structure with the same properties. The only difference between the two sections is the optical light shield. The optical centres of all pixels in the image section form a square grid. The charge is generated and integrated in this section. Output registers are located below the storage section. The output amplifiers Y and Z are not used in Frame Transfer mode and should be connected as not-used amplifiers. After the integration time the charge collected in the image section is shifted to the storage section. The charge is read out line by line through the lower output register. The left and the right half of each output register can be controlled independently. This enables either single or multiple read-out. During vertical transport the C3 gates separate the pixels in the register. The letters W, X, Y and Z are used to define the four quadrants of the sensor. The central C3 gates of both registers are part of the W and Z quadrants of the sensor. Both upper and lower registers can be used for vertical binning. Both registers also have a summing gate at each end that can be used for horizontal binning. Figure 2 shows the detailed internal structure.
IMAGE SECTION Image diagonal (active video only) Aspect ratio Active image width x height Pixel width x height Geometric fill factor Image clock pins Capacity of each clock phase Number of active lines Number of black reference lines Number of dummy black lines Total number of lines Number of active pixels per line Number of overscan (timing) pixels per line Number of black reference pixels per line Total number of pixels per line 17.38 mm 1:1 2 12.288 x 12.288 mm 12x12 m2 100% A1, A2, A3, A4 2.5nF per pin 1024 2 4 1030 1024 8 (2x4) 40 (2x20) 1072
STORAGE SECTION Storage width x height Cell width x height Storage clock phases Capacity of each clock phase Number of cells per line Number of lines 12.864 x 12.360 mm2 12x12 m2 B1, B2, B3, B4 2.5nF per pin 1072 1030
OUTPUT REGISTERS Output buffers (three-stage source follower) Number of registers Number of dummy cells per register Number of register cells per register Output register horizontal transport clock pins Capacity of each C-clock phase Overlap capacity between neighbouring C-clocks Output register Summing Gates Capacity of each SG Reset Gate clock phases Capacity of each RG 4 (one on each corner) 2 (one above, one below) 14 (2x7) 1072 C1, C2, C3 60pF per pin 20pF 4 pins (SG) 15pF 4 pins (RG) 15pF
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Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
RD RG
7 dummy pixels
OG SG C2 C1 C3 C2 C1 C3 C2 A1 A2 A3 A4
20 black & 4 timing columns
C1 C3 C2 C1 C3 C2 C1 C3 C2 C1
1K image pixels
C3 C2 C1
20 black & 4 timing columns
C3 C2 C1 C3 C2 C1 C3 C2 C1 A1 A2 A3 A4 C3 C2 C1
7 dummy pixels
C3 C2 C1 SG OG
RD RG
OUT_Z (not used)
OUT_Y (not used)
A1 A2 A3 A4 A1 A2 A3 A4
6 black lines
A1 A2 A3 A4
IMAGE
1K active images lines FT CCD
A1 A2 A3 A4
One Pixel
A1 A2 A3 A4 B1 B2
A1 A2 A3 A4 B1 B2 B3 B4
SG: OG: RG: RD:
summing gate output gate reset gate reset drain
B3 B4
A1 B1 B2 B3 B4 B1 B2 B3 B4
1K storage lines
A1 B1 B2 B3 B4
STORAGE
6 black lines
B1 B2 B3 B4
B1 B2 B3 B4 B1 C3 C2 C1 C3 C2 C1 C3 C2 C1 C3 C2 C1 C3 C2 C1 C3 C3 C2 C1 C3 C2 C1 C3 C2 C1
B1 B2 B3 B4 B1 C3 C2 C1 C3 C2 C1 C3
OUT_W
OG SG C2 C1 RG RD
OUT_X
C2 C1 SG OG RG RD
column 1
column 24 + 1
column 24 + 1K
column 24 + 1K + 24
A1, A2, A3, A4: clocks of image section
B1, B2, B3, B4: clocks of storage section Figure 2 - Detailed internal structure
C1, C2, C3: clocks of horizontal registers
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Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Specifications
ABSOLUTE MAXIMUM RATINGS1 GENERAL: storage temperature ambient temperature during operation voltage between any two gates DC current through any clock phase (absolute value) OUT current (no short circuit protection) VOLTAGES IN RELATION TO VPS: VNS, SFD, RD VCS, SFS all other pins VOLTAGES IN RELATION TO VNS: SFD, RD VCS, SFS, VPS all other pins -55 -40 -20 -0.2 0 -0.5 -8 -5 -15 -30 -30 MIN. +80 +60 +20 +2.0 10 +30 +5 +25 +0.5 +0.5 +0.5 MAX. C C V A mA V V V V V V UNIT
DC CONDITIONS2 VNS VPS SFD SFS VCS OG RD
3
MIN. [V] 18 1 16 -5 4 13
TYPICAL [V] 24 3 20 0 0 6 15.5
MAX. [V] 28 7 24 3 8 18
MAX. [mA] 15 15 4.5 1 -
N substrate P substrate Source Follower Drain Source Follower Source Current Source Output Gate Reset Drain
AC CLOCK LEVEL CONDITIONS2 IMAGE CLOCKS: A-clock amplitude during integration and hold A-clock amplitude during vertical transport (duty cycle=5/8)4 A-clock low level Charge Reset (CR) level on A-clock 5 STORAGE CLOCKS: B-clock amplitude during hold B-clock amplitude during vertical transport (duty cycle=5/8) OUTPUT REGISTER CLOCKS: C-clock amplitude (duty cycle during hor. transport = 3/6) C-clock low level Summing Gate (SG) amplitude Summing Gate (SG) low level OTHER CLOCKS: Reset Gate (RG) amplitude Reset Gate (RG) low level Charge Reset (CR) pulse on Nsub
MIN.
TYPICAL
MAX.
UNIT
8 10 -5 8 10 4.75 2
10 14 0 -5 10 14 5 3.5 10 3.5 10 3 10 5.25 10
V V V V V V V V V V V V V
5
5
10 10
0
During Charge Reset it is allowed to exceed maximum rating levels (see note5). All voltages in relation to SFS. 3 To set the VNS voltage for optimal Vertical Anti-Blooming (VAB), it should be adjustable between minimum and maximum values. 4 Three-level clock is preferred for maximum charge; the swing during vertical transport should be 4V higher than the voltage during integration. A two level clock (typically 10V) can be used if a lower maximum charge handling capacity is allowed. 5 Charge Reset can be achieved in two ways: * The typical CR level is applied to all image clocks simultaneously (preferred). * The typical A-clock low level is applied to all image clocks; for proper CR, an additional Charge Reset pulse on VNS is required. This will also affect the charge handling capacity in the storage areas.
2
1
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Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Timing diagrams (for default operation)
AC CHARACTERISTICS Horizontal frequency (1/Tp) 1 Vertical frequency Charge Reset (CR) time Rise and fall times: image clocks (A) storage clocks (B) register clocks (C) 2 summing gate (SG) reset gate (RG)
1 2
MIN. 0 0 2 10 10 3 3 3
TYPICAL 18 450 5 20 20 5 5 5
MAX. 40 1000
UNIT MHz kHz s ns ns ns ns ns
1/6 Tp 1/6 Tp 1/6 Tp
Tp = 1 clock period Duty cycle = 50% and phase shift of the C clocks is 120 degrees.
Line Timing
SSC B1 B2 B3 B4 CR * AHigh VD BLC H L H L H L H L H L H L H L H L H L 105Tp 19Tp 25Tp 14Tp 15Tp 24Tp 34Tp 2 Tp 15Tp 15Tp 101 Tp 105 Tp
30Tp
141Tp
Pixel Timing
SSC C1 C2 C3 SG RG H L H L H L H L H L H L 1079 pixels 1Tp
Tp / 6
Tp = 1 clock period = 1 / 18MHz = 55.56ns Pixel output sequence: 7 dummy, 20 black, 4 timing, 1024 active, 4 timing, 20 black * During AHigh = H the phiA high level is increased from 10V to 14V
Line Time: 1184 x Tp = 65.7s
VD: Frame pulse CR: Charge Reset BLC: Black Level Clamp B1 to B4: Vertical storage clocks
C1 to C3: Horizontal register clocks SSC: Start-Stop C-clocks SG: Summing gate RG: Reset gate
Figure 3 - Line and pixel timing diagrams
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Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Frame Timing
Sensor Output H SSC L H A1, A2, A3 L H A4 L H B1 L H B2, B3, B4 L H CR L H * Ahigh L H VD L H BLC L H EXT. SHUTTER L
1019 1020 1021 1022 1023 1024
Black B B B B B 1 2 3 4
Frame Shift
Integration Time
Frame Shift Timing
Tframe shift = 1027 x 8 x N clock periods H L H L H L H L H L H L H L H L A1 A2 A3 A4 B1 B2 B3 B4
1
1
8 phases correspond with 2 line shifts N= Horizontal freq. , Vertical freq. x 8 for example: 18MHz 450kHz x 8 =5
VD: Frame pulse CR: Charge Reset BLC: Black Level Clamp A1 to A4: Vertical image clocks
B1 to B4: Vertical storage clocks C1 to C3: Horizontal register clocks SSC: Start-Stop C-clocks SG: Summing gate RG: Reset gate Figure 4 - Frame timing diagrams
1999 September
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Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Line timing
SSC
B1
B2
B3
B4
--> time Y / Div. : 10V (B1, B2, B3, B4); 5V (SSC)
Figure 5 - Vertical readout
Pixel timing
C1
C2
C3
SG
RG --> time Y / Div. : 5V (C1, C2, C3); 10V (SG, RG)
Figure 6 - Start horizontal readout
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Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Performance
The test conditions for the performance characteristics are as follows: * All values are measured using typical operating conditions. * VNS is adjusted as low as possible while maintaining proper Vertical Anti-Blooming. * Sensor temperature = 60C (333K). * Horizontal transport frequency = 18MHz. * Vertical transport frequency = 450kHz (unless specified otherwise). * Integration time = 10ms (unless specified otherwise). * The light source is a 3200K lamp with neutral density filters and a 1.7mm thick BG40 infrared cut-off filter. For Linear Operation measurements, a temperature conversion filter (Melles Griot type no. 03FCG261, -120 mired, thickness: 2.5mm) is applied.
LINEAR OPERATION Linear dynamic range
1
MIN. 4200:1
TYPICAL
MAX.
UNIT
Charge Transfer Efficiency 2 vertical Charge Transfer Efficiency horizontal Image lag Smear
3 2
0.999995 0.999999 0 -39 65 180 25 250 30 2.5 0 % dB % kel/lux*s % % % V mW
Resolution (MTF) @ 42 lp/mm Responsivity Quantum efficiency @ 530 nm White Shading 4 Random Non-Uniformity (RNU)
5
0.3 18 24 410
5 28
VNS required for good Vertical Anti-Blooming (VAB) Power dissipation at 15 frames/s
1 2 3
4
5
Linear dynamic range is defined as the ratio of Q lin to read-out noise (the latter reduced by Correlated Double Sampling). Charge Transfer Efficiency values are tested by evaluation and expressed as the value per gate transfer. Smear is defined as the ratio of 10% of the vertical transport time to the integration time. It indicates how visible a spot of 10% of the image height would become. White Shading is defined as the ratio of the one- value of the pixel output distribution expressed as a percentage of the mean value output (low pass image). RNU is defined as the ratio of the one- value of the highpass image to the mean signal value at nominal light.
Linear Dynamic Range
20,000 18,000 16,000 14,000
LDR 35C
45C 55C
12,000 10,000 8,000 6,000 4,000 2,000 0 0 5 10 15 20 25 Hor. Frequency (MHz) 30 35 40
Figure 7 - Typical Linear dynamic range vs. horizontal read-out frequency and sensor temperature
1999 September
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Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Maximum Read-out Speed
80 70 60 50 40 30 20 10 0 0 10 20 30 40 50 60 70 80 90 100
Integration time (ms) 2 outputs
Images/sec.
1 output
Figure 8 - Maximum number of images/second versus integration time
Quantum Efficiency
30 25
Quantum efficiency (%)
20 15 10 5 0 400
450
500
550
600
650
700
750
800
Wavelength (nm)
Figure 9 - Quantum efficiency versus wavelength
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Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
LINEAR/SATURATION Full-well capacity saturation level (Qmax) 1 Full-well capacity shading (Qmax, shading) 2 Full-well capacity linear operation (Qlin) Charge handling capacity 4 Overexposure handling
5 3
MIN.
TYPICAL
MAX.
UNIT
250
500 10
600 50
kel. % kel. kel. x Qmax level
200
350 600
100
200
1 2
Qmax is determined from the lowpass filtered image. Qmax, shading is the maximum difference of the full-well charges of all pixels, relative to Qmax. 3 The linear full-well capacity Qlin is calculated from linearity test (see dynamic range). The evaluation test guarantees 97% linearity. 4 Charge handling capacity is the largest charge packet that can be transported through the register and read-out through the output buffer. 5 Overexposure over entire area while maintaining good Vertical Anti-Blooming (VAB). It is tested by measuring the dark line.
Charge Handling vs. Integration/Transport Voltage
600
10V/14V
500
Output Signal (kel.) 9V/13V
400 300 200 100 0
8V/12V
1
2
3 4 Exposure (arbitrary units)
5
6
Figure 10 - Charge handling versus integration/transport voltage
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Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
OUTPUT BUFFERS
MIN.
TYPICAL
MAX.
UNIT
Conversion factor Mutual conversion factor matching (ACF)1 Supply current Bandwidth Output impedance buffer (Rload = 3.3k, Cload = 2pF)
1
6
8 0 4 110 400
12 2
V/el. V/el. mA MHz
Matching of the four outputs is specified as ACF with respect to reference measured at the operating point (Qlin/2).
DARK CONDITION
MIN.
TYPICAL
MAX.
UNIT pA/cm2 nA/cm2 el. el.
Dark current level @ 30 C Dark current level @ 60 C Fixed Pattern Noise 1 (FPN) @ 60 C RMS readout noise @ 9MHz bandwidth after CDS
1
20 0.3 15 25
30 0.6 25 30
FPN is the one- value of the highpass image.
Dark Current
1000
Dark Current (pA/cm2)
100
10
1 0 10 20 30
Temp. (oC)
40
50
60
Figure 11 - Dark current versus temperature
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Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Application information
Current handling One of the purposes of VPS is to drain the holes that are generated during exposure of the sensor to light. Free electrons are either transported to the VRD connection and, if excessive (from overexposure), free electrons are drained to VNS. No current should flow into any VPS connection of the sensor. During high overexposure a total current 10 to 15mA through all VPS connections together may be expected. The PNP emitter follower in the circuit diagram (figure 12) serves these current requirements.
VNS drains superfluous electrons as a result of overexposure. In other words, it only sinks current. During high overexposure a total current of 10 to 15mA through all VNS connections together may be expected. The NPN emitter follower in the circuit diagram meets these current requirements. The clamp circuit, consisting of the diode and electrolytic capacitor, enables the addition of a Charge Reset (CR) pulse on top of an otherwise stable VNS voltage. To protect the CCD, the current resulting from this pulse should be limited. This can be accomplished by designing a pulse generator with a rather high output impedance. The CCD output buffer can easily be destroyed by ESD. By using this emitter follower, this danger is suppressed; do NOT reintroduce this danger by measuring directly on the output pin of the sensor with an oscilloscope probe. Instead, measure on the output of the emitter follower. Slew rate limitation is avoided by avoiding a toosmall quiescent current in the emitter follower; about 10mA should do the job. The collector of the emitter follower should be decoupled properly to suppress the Miller effect from the base-collector capacitance. A CCD output load resistor of 3.3k typically results in a bandwidth of 110MHz. The bandwidth can be enlarged to about 130MHz by using a resistor of 2.2k instead, which, however, also enlarges the on-chip power dissipation.
Device protection The output buffers of the FTT1010-M are likely to be damaged if VPS rises above SFD or RD at any time. This danger is most realistic during power-on or power-off of the camera. The RD voltage should always be lower than the SFD voltage.
Never exceed the maximum output current. This may damage the device permanently. The maximum output current should be limited to 10mA. Be especially aware that the output buffers of these image sensors are very sensitive to ESD damage. Because of the fact that our CCDs are built on an n-type substrate, we are dealing with some parasitic npn transistors. To avoid activation of these transistors during switch-on and switch-off of the camera, we recommend the application diagram of figure 12.
Decoupling of DC voltages All DC voltages (not VNS, which has additional CR pulses as described above) should be decoupled with a 100nF decoupling capacitor. This capacitor must be mounted as close as possible to the sensor pin. Further noise reduction (by bandwidth limiting) is achieved by the resistors in the connections between the sensor and its voltage supplies. The electrons that build up the charge packets that will reach the floating diffusions only add up to a small current, which will flow through VRD. Therefore a large series resistor in the VRD connection may be used. Outputs To limit the on-chip power dissipation, the output buffers are designed with open source outputs. Outputs to be used should therefore be loaded with a current source or more simply with a resistance to GND. In order to prevent the output (which typically has an output impedance of about 400) from bandwidth limitation as a result of capacitive loading, load the output with an emitter follower built from a high-frequency transistor. Mount the base of this transistor as close as possible to the sensor and keep the connection between the emitter and the next stage short.
Unused sections To reduce power consumption the following steps can be taken. Connect unused output register pins (C1...C3, SG, OG) and unused SFS pins to zero Volts. More information Detailed application information is provided in the application note AN01 entitled `Camera Electronics for the mK x nK CCD Image Sensor Family'.
1999 September
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Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Device Handling
An image sensor is a MOS device which can be destroyed by electrostatic discharge (ESD). Therefore, the device should be handled with care. Always store the device with short-circuiting clamps or on conductive foam. Always switch off all electric signals when inserting or removing the sensor into or from a camera (the ESD protection in the CCD image sensor process is less effective than the ESD protection of standard CMOS circuits). Being a high quality optical device, it is important that the cover glass remain undamaged. When handling the sensor, use fingercots. When cleaning the glass we recommend using ethanol (or possibly water). Use of other liquids is strongly discouraged: * if the cleaning liquid evaporates too quickly, rubbing is likely to cause ESD damage. * the cover glass and its coating can be damaged by other liquids. Rub the window carefully and slowly. Dry rubbing of the window may cause electro-static charges or scratches which can destroy the device.
VSFD CR pulse 0 BC 850C 0.5-1mA 100nF BAT74 BAT74 SFD 100nF + 2mA 1uF VNS OUT 100
keep short <10mm!
keep short! BFR 92A output for preprocessing 10mA <7pF! 100nF
BC 850C
3.3k
1k
0.5-1mA
27 BAT74 Schottky!
0.5-1mA BC 860C
VPS
15 BAT74 Schottky! 10k
VCS
Figure 12 - Application diagram to protect the FTT1010-M
100nF 100nF
100nF
10k
VRD
VOG
100nF
10k
1999 September
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Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Pin configuration
The FTT1010-M is mounted in a Pin Grid Array (PGA) package with 76 pins in a 15x13 grid of 40.00 x 40.00 mm2. The position of pin A1 is marked with a gold dot on top of the package. The clock phases of quadrant W are internally connected to X, and the clock phases of Y are connected to Z.
Symbol VNS VNS VNS VNS VNS VPS SFD SFS VCS OG RD A1 A2 A3 A4 B1 B2 B3 B4 C1 C2 C3 SG RG OUT NC
Name N substrate N substrate N substrate N substrate N substrate P substrate Source Follower Drain Source Follower Source Current Source Output Gate Reset Drain Image Clock (Phase 1) Image Clock (Phase 2) Image Clock (Phase 3) Image Clock (Phase 4) Storage Clock (Phase 1) Storage Clock (Phase 2) Storage Clock (Phase 3) Storage Clock (Phase 4) Register Clock (Phase 1) Register Clock (Phase 2) Register Clock (Phase 3) Summing Gate Reset Gate Output Not connected
Pin # W A12 D11 E11 E12 C11 A13 A10 A11 B13 B12 D13 C12 D12 C13 B9 B8 A8 B10 A9 B11 B7
Pin # X A3 B2 D3 E2 E3 C3 A1 B5 A4 B1 B3 D1 C2 D2 C1 A6 A7 B6 A2 A5 B4
Pin # Y J2 F3 G3 J1 J4 J3 H1 H2 F1 G2 F2 G1 H5 H6 J6 H4 J5 H3 H7
Pin # Z F11 H12 J11 G11 J13 H9 J10 H13 H11 F13 G12 F12 G13 J8 J7 H8 J12 J9 H10
13 12 11 10 9 J H G F
SFD OG SG VNS VNS RD VCS OUT RG SFS
8
C1 C3
7
C2 NC
6
C3 C2
5
RG C1
4
SFS SG
3
VCS OUT
2
VNS RD
1
SFD OG
J H G F
A4
A2
VPS
TOP
VPS
A2 A3
A4 A1
A1
A3
VNS
VNS
Z
B4
IMAGE
Y X
VNS VNS
B4
W
E D C B A
B1 B4 VNS VNS B3 VNS
STORAGE
B1
B1
E
B1 B4
VNS
B3 B2
D C B A
B2
VPS
FTT1010-M
SG SFS C1 RG C2 C3 NC C2 C3 C1 SFS RG OUT VCS
VPS
OG SFD
RD VNS
OUT VCS
RD VNS
VNS SG
OG SFD
13 12 11 10 9
8
7
6
5
4
3
2
1
Figure 13 - FTT1010-M pin configuration (top view)
1999 September
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Philips Semiconductors
Product specification
Frame Transfer CCD Image Sensor
FTT1010-M
Package information
Top cover glass to top chip 2.4 0.25 Chip - bottom package 1.7 0.15
SENSOR CRYSTAL COVER GLASS
Chip - cover glass 1.3 0.20
A ZONE
Cover glass 1.0 0.05
8.9
Image sensor chip
23 0.33
40 0.40
1.4 / 100
TOP VIEW INDEX MARK PIN 1
26 0.15 40 0.40
20 0.10
COVER GLASS
1.27 0.15
(2.54)
STAND-OFF PIN
0.46 0.05
4.57 0.15
A is the center of the image area. Position of A: 26 0.15 to left edge of package 20 0.10 to bottom of package Angle of rotation: less than 10 Sensor flatness: < 7 m (P-V) Cover glass: Corning 7059 Thickness of cover glass: 1.00 0.05 Refractive index: nd = 1.53 Single sided AR coating inside (430-660 nm) All drawing units are in mm 16
BOTTOM VIEW
35.56 0.20
Figure 14 - Mechanical drawing of the PGA package of the FTT1010-M
1999 September
30.48 0.20
The sensors can be ordered using the following codes:
FTT1010-M sensors
Description
FTT1010-M/TG FTT1010-M/EG FTT1010-M/IG FTT1010-M/HG
Quality Grade
Test grade Economy grade Industrial grade High grade
Order Code
9922 157 35031 9922 157 35051 9922 157 35021 9922 157 35011
You can contact the Image Sensors division of Philips Semiconductors at the following address: Philips Semiconductors Image Sensors Internal Postbox WAG-05 Prof. Holstlaan 4 5656 AA Eindhoven The Netherlands phone fax +31 - 40 - 27 44 400 +31 - 40 - 27 44 090
www.semiconductors.philips.com/imagers/
lmtb
Philips Semiconductors
TRAD
Philips reserves the right to change any information contained herein without notice. All information furnished by Philips is believed to be accurate. (c) Philips Electronics N.V. 1999 9922 157 35011
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